Silicon Based Integrated Circuit Technology Engineering Essay

Silicon Based Integrated Circuit Technology Engineering Essay

Abstract- The present paper treats the C nanotube field consequence transistors ( CNFETs ) in footings of new development as a possible hereafter basic component for beyond CMOS engineering used in extremist high graduated table integrating ( ULSI ) with their first-class current capablenesss, ballistic conveyance operation and superior thermic conductions. We have used here a SPICE compatible theoretical account of CNTFET with the circuit parametric quantities extracted from quantum mechanical equations and so employed it in planing 6-Transistor SRAM cell utilizing trial bench coding and so implementing in SPICE3 utilizing 32nm engineering to analyse its simulation based appraisal of circuit public presentation in footings of simulation clip, power dissipation etc.

Keywords- CNTFET, 6-T SRAM Cell, Test bench codification in SPICE3.

I. Introduction

Silicon-based incorporate circuit engineering is nearing its physical bound as the device dimensions graduated table to the nanometre government. In the station Si epoch, C nanotube field consequence transistor ( CNTFET ) is a promising campaigner for future integrated circuits because of its first-class belongingss like near ballistic conveyance, high bearer mobility ( 103-104 cm2/VA·s ) in semiconducting C nanotube ( CNTs ) [ 1, 2 ] and easy integrating of high-k dielectric stuff ensuing in better gate electrostatics.

CNTFET is now treated as the highest precedence to plan a fast and power-efficient memory constructions to increase the public presentation of overall system in footings of ballistic conveyance operation and low current under OFF status makes them really attractive for the high public presentation and increased integrating complexness of SRAM arrays design in trial bench coding utilizing SPICE.

In this paper, planing of 6T SRAM cell based CNTFETs is done utilizing trial bench coding in SPICE and public presentation parametric quantity in footings of velocity of operation and power dissipation are evaluated and compared with conventional MOS devices.

In Section II of this paper, a brief reappraisal of the mold of CNT field consequence transistor is presented. The designs of 6-T CNTFET SRAM cell in SPICE3 trial bench are explained in Section III. Section IV includes its execution and eventually, Section V concludes this paper.

II. MODEL FOR CNTFET

CNTs are used in the channel part of the CNTFET. Different types of CNTFET have been demonstrated in the literature. There are chiefly two types of CNTFET: ( a ) Schottky barrier CNTFET ( SB-CNTFET ) and ( B ) MOSFET-like CNTFET as shown in the fig. below [ 3 ]

In SB-CNTFET the channel is made of intrinsic semiconducting CNT and direct contacts of the metal with the semiconducting nanotubes are made for beginning and drain parts. The device works on the rule of direct burrowing through the Schottky barrier ( SB ) at the source-channel junction. The barrier-width is modulated by the application of gate electromotive force, and therefore, the transconductance of the device is controlled by the gate electromotive force.

In MOSFET-like CNTFET doped CNTs are used for the beginning and drain parts and channel is made of intrinsic semiconducting CNT. A tunable CNTFET with electrical doping is besides proposed. It works on the rule of barrier-height transition by the application of gate potency.

In this work we use here MOSFET like CNTFET theoretical account to plan memory cells. First we present the compact theoretical account of MOSFET like CNTFET. We have developed this theoretical account utilizing quantum mechanical equations. It is a surface potential-based SPICE compatible theoretical account which is used to plan a extremely incorporate 6-T SRAM cell.

Figure.1. Schematic of SPICE compatible CNTFET theoretical account, where CGS is gate to beginning electrical capacity, CGD is gate to run out electrical capacity, RD is drain opposition, RS is beginning opposition, VFB is flat-band electromotive force, and ID is drain current.

This theoretical account is applicable to a scope of CNTs with diameter between 1 to 3 nanometers. The computational process to measure the drain current ID and the entire channel charge QCNT is illustrated in Fig. 2. The chief measures used in the theoretical account are the surface possible I?S and the specific electromotive force I?i ( S/D ) that depends on the surface potency, the bomber set energy degree I”p and the beginning ( drain ) Fermi degree ( Intrinsic Fermi degree ) I?S/D. The specific electromotive force is given by

For one = beginning ( S ) , and drain ( D ) . Here, kilobit is the Boltzmann invariable, and T is the operating temperature. When the conductivity set lower limit for the first bomber set is set to half the nanotube set spread I”1 ( I”1a‰? 0.45/diameter ( in electron volt ) )

Then the pth equilibrium conduction-band lower limit I”p is given by the above look.

Figure.2.Structure of CNTFET compact theoretical account.

An of import measure in this theoretical account formation is to acquire the control potency or the surface possible I?S with gate prejudice electromotive force. The cognition of I?S is required to acquire the specific electromotive force I? . This allows us to find the needed end product parameter drain current ID and the entire charge QCNT. In the undermentioned estimate is proposed.

Where the parametric quantity I± is given by

Where I±0, I±1 and I±2 are dependent on both CNT diameter and gate oxide thickness. The entire drain current ID is given by

Where P is the figure of sub sets, vitamin E is the charge of negatron and H is the Planck invariable.

The gate prejudice VG required to bring forth the false I?S based on the electrostatic electrical capacity given by

Where CINS is the dielectric electrical capacity. The complete charge relation can be obtained by the amount of charges contributed by all the conductivity bands that is populated by drain and beginning Fermi degrees. So in this manner we obtain a simplified SPICE-compatible theoretical account of CNTFET and p-type and n-type CNTFET can be obtained by merely changing the mutual opposition of the mutual opposition gate ( PG ) . In the staying portion of the paper we shall utilize the SPICE compatible theoretical account CNTFET in planing 6-transistor CNTFET based SRAM cell. Based on a chiral vector ( n, m ) , a SWCNT could be carry oning or semiconducting. The current-voltage ( I-V ) features of the CNTFET with different channel lengths, is shown in Figure 3, and they are similar to those of MOSFET which makes CNTFET a good campaigner for ultra-low power applications. CNTFETs have the capableness of puting the needed threshold electromotive forces by taking proper diameter for the nanotubes [ 4 ] . For e.g. the threshold electromotive force of the CNTFET holding ( 19, 0 ) CNTs is 0.289 V because the DCNT of ( 19, 0 ) CNT is 1.49 nanometer.

Figure.3.Current-Voltagecharacteristics for MOSFET like CNTFET

Figure 4. CNTFETs based 6T- SRAM

III. 6T SRAM CELL DESIGN USING CNTFET

( A ) . 6T SRAM CELL

The conventional [ six-transistor ( 6T ) ] SRAM cell construction based on CNTFETs which is the nucleus storage component of most registry file and cache designs, is shown in Figure 4. It has four transistors P1, P2, N1 and N2 form two cross-coupled inverters for storage and two base on balls transistors N3 and N4 signifier as a combination of read/write port. With the aggressive grading in CMOS engineering, at ultra-low power supply, the usage of 6T SRAM cell leads to legion critical jobs like hapless stableness, high power ingestion etc. In this instance CNTFETs could be a good option with high stableness and high denseness for high denseness memories.

The BIT and BIT saloon lines in Figure 4 are pre-charged before any read operation. During read operation, the WL spot is “ high ” which makes both the transistor N3 and N4 to be turned ON and the stored informations in SRAM cell is read. But this stored information may alter due to a read-upset job which is as follows. Suppose that the SRAM cell is presently hive awaying a “ 1 ” so that Q is “ 1 ” and Q_bar is “ 0 ” . When WL spot is high and transistor N3 and N4 are ON, so voltage degree at node Q_bar will lift. In this instance, an appropriate device sizing ratio between N1 and N3 is desired to restrict the electromotive force at node Q_bar to be less than threshold electromotive force ( Vth ) so that the stored informations will non differ during the read operation.

For the dependable write operation, the pull-up transistor of SRAM cell should non be really carry oning. Suppose that the WL spot is high, SRAM cell is presently keeping “ 1 ” and system is traveling to compose “ 0 ” into SRAM cell. In this instance the electromotive force degree at node Q2 in Figure 4 will diminish merely when the base on balls transistor N4 is stronger than the pull up transistor P2.

( B ) . TEST BENCH CODING IN SPICE3 TO DESIGN 6-T CNTFET BASED SRAM

The trial bench to imitate the SRAM cell based on the proposed SPICE-CNT transistor theoretical account is shown below in list.1. In this book line 3-6 provide the mention electromotive force and input wave form. The SRAM net list shown in lines 8-20 is a typical SPICE description which connects constituents and nodes for analysis. Note that the transistor theoretical account given by the lines 17 and 18 usage the developed non- ballistic CNT transistor theoretical account based on quantum mechanical equations and parametric quantity estimate method. A transeunt measuring is applied and the end product phase is shown in lines 22-25.

1 CNT SRAM cell end product features

2.opt no page

3 Vds 1 0 D=.5

4 Vgs 2 0 PWL 0 0 1PS.5 600PS.5 601PS 0

5 Vgs 2 3 PWL 0 0 1PS.5 300PS.5 301PS 0 600PS 0 601PS.5 900PS.5 901PS 0

6 Vgs 3 0 PWL 0.5 1 PS.0 300PS 0 301PS.5 600PS.5 601PS 0 900PS 0 901PS.5

7

8 *Ef is the Fermi degree, Defense Intelligence Agency is the diameter of the CNT

9 * default Si dioxide thickness to is 15nm

10 * and comparative inactive permittivity peers to 3.9

11 N2 10 9 0 0 mod1 ad=10f as=10f diameter =1.49e-9 Ef= -0.3

12 P2 10 9 1 1 mod2 ad=10f as=10f dia =1.49e-9 Ef= -0.3

13 N1 9 10 0 0 mod1 ad=10f as=10f dia =1.49e-9 Ef= -0.3

14 P1 9 10 1 1 mod2 ad=10f as=10f dia =1.49e-9 Ef= -0.3

15 N3 4 2 10 10 mod1 ad=10f as=10f dia =1.49e-9 Ef= -0.3

16 N4 3 2 9 9mod 1 ad=10f as=10f dia =1.49e-9 Ef= -0.3

17.model mod1 ncnt Vto=0.15 nsub=1.0A-e15 Aµo=550 tox=15e-9

18.model mod2 pcnt Vto=-0.15 nsub=1.0A-e15 Aµo=150 tox=15e-9

19 C1 9 0.5 degree Fahrenheit

20 C2 10 0.1f

21

22.dc Vgs 0.0.5.1

23.trans 2PS 1200PS

24.plot District of Columbia V ( Q ) [ V ( Q_bar ) ]

25.end

List.1. Test bench cryptography of CNTFET based SRAM cell utilizing SPICE

1V. Execution OF CNTFET BASED SRAM CELL IN SPICE3

The SRAM cell is performed as expected. As the word line ( WL ) is asserted, informations can be written into the memory cell by using proper values to seize with teeth lines ( BIT and BIT saloon ) . After the authorship period the SRAM cell comes into base by position while the word line is set to 0, and the memory cell will hive away the informations until following on the job period. The simulation clip for CNTFET based SRAM cell is short with mean CPU clip of circa 1sec. In this paper, circuit simulation uses the Stanford CNTFET theoretical account [ 9-11 ] and 32nm nano engineering for CMOS to measure the public presentation of CNTFET based SRAM cells in term of signal to resound border by plotting against the electromotive force between Q and A?QA?A? as shown in Fig.5. The end product current feature of SRAM cell ( Fig.6 ) has besides been obtained to analyze the power ingestion of the CNTFET based SRAM cell and compare it with the power dissipation of normal CMOS based SRAM cell as shown in Fig.7.

Power dissipation of CNTFET based SRAM cell is estimated by the look given below:

PSC=1/2 VDD IPEAK terrestrial time f. N

Where VDD stand for the drain to beginning electromotive force ( 0.5V for this simulation ) , f is the operation frequence ( 3.33GHz ) , tt represent the passage clip for input ( 0.1nsec ) , Ipeak is the maximal impregnation current of the CNT transistor in the SRAM cell ( 1.6AµA ) and n is the no. of transistor ( 6 transistor ) used in the SRAM cell. With the parametric quantities derived from the simulation the power ingestion PSC can be estimated to be circa 0.8AµW for the fake SRAM cell, which dissipated really little energy ( around 2.4A-10-16J per switch for the CNT SRAM cell )

Figure.5. SNM ( Signal to resound border ) of the 6T SRAM cell

Figure.6. Operation current features of SRAM cell based on SPICE compatiiable CNTFET theoretical account

Figure.7. Comparative analysis of power dissipation

V. CONCLUSION

CNTFET based SRAM cell was simulated utilizing the trial bench coding written in SPICE3 and they wholly performed as expected while necessitating small CPU clip. This shows great potency for the proposed SPICE3 theoretical account to analyse circuit with big figure of CNT transistor. Simulation consequence besides showed that the SPICE3 theoretical account could work with low supply electromotive force while keeping high operation velocity. Comparison consequence showed that the circuit based on developed SPICE3 CNT transistor theoretical account consumes much less power than the convectional MOS devices. Consequence showed that proposed SPICE3 implemented CNTFET based SRAM cell is capable of capturing the consequence of parametric quantity fluctuation on CNT based logic circuit public presentation.